/*
*   双口RAM，基于模板推导
*   16384bits
*   1.7777777777777777xM9K
*/
module dpram_13_2  //地址宽度_数据宽度 
(

    input [1:0] data_a, data_b, 
    input [12:0] addr_a, addr_b,
    input we_a, we_b, clk_a, clk_b,
    output reg [1:0] q_a, q_b
);

    reg [1:0] ram[8191:0];  //

    //第一个端口
    always @ (posedge clk_a)
    begin
        // Port A 
        if (we_a) 
        begin
            ram[addr_a] <= data_a;
            q_a <= data_a;
        end
        else 
        begin
            q_a <= ram[addr_a];
        end 
    end

   //第二个端口
    always @ (posedge clk_b)
    begin
        // Port B 
        if (we_b) 
        begin
            ram[addr_b] <= data_b;
            q_b <= data_b;
        end
        else 
        begin
            q_b <= ram[addr_b];
        end 
    end

endmodule
